1. Field of the Disclosure
The present disclosure generally relates to memory, and, more particularly, to mapping of physical addresses to memory locations in a memory with one or more banks.
2. Description of the Related Art
Many memory architectures are organized into one or more banks, both at the structural level and the silicon implementation level. Typically, a physical address is uniquely mapped to a corresponding row of a corresponding bank. The mapping of physical addresses to corresponding bank/row locations generally is selected at design time and remains fixed. Certain memory architectures, such as dynamic random access memory (DRAM)-based architectures and phase change memory architectures, have certain set-up requirements that cause successive accesses to different rows of the same bank to take considerably longer than successive accesses to the same row. Further, some memory architectures utilize a row buffer to buffer data at an activated row of a bank, thereby allowing a successive access to a different bank at the same row to process with respect to the row buffer, rather than requiring direct access to the bank itself. In view of the advantages of having successive memory accesses directed to the same row, some software applications adjust the data layout in memory so as to render successive accesses by a software application to the same row more likely. However, this approach requires software modifications in the operating system, compiler, or runtime software, as welt as requiring the software designer to have foreknowledge of both the likely access pattern for the data and the memory address redirection needed to optimize the access pattern. Moreover, this approach only benefits those software applications specifically designed and compiled in this manner.